The integrated circuit chip and the package are an inseparable whole. No chip can work normally without packaging. Packaging is essential for chips. With the advancement of IC production technology, packaging technology is constantly updated, and each generation of IC is closely linked to a new generation of IC packaging technology. . In the 21st century, as semiconductor technology gradually approaches the limit of silicon process size, semiconductor technology has entered the “post-Moore’s Law” era, and advanced packaging technology has achieved unprecedented development.
SiP creates traditional “ASIC” at low cost
Often to advance the design, the industry uses ASIC technology to integrate different functions onto a single chip. But as IC manufacturing processes continue to scale, ASIC scaling becomes more difficult, the power/performance benefits shrink, and the cost of tape-out becomes higher. Advanced packaging is beginning to become another important innovation direction for foundries and packaging houses.
In a way, SiP is a traditional “ASIC” built at a lower cost. SiP modules can integrate chips and passive devices of different processes and materials into a system to achieve the functional requirements of Electronic products.
Most chips still use mature and commercial packaging technology. Even so, advanced packaging technology that can provide smaller size and better electrical performance has been favored by more and more IC suppliers. In addition, the need for miniaturization, which combines shorter development time and cost-effectiveness, is driving the mass adoption of SiP. According to Yole, the SiP market is expected to grow to $1.88 billion by 2025, with a CAGR of 6% during the forecast period (2019-2025).
SiP is currently mainly used in TWS headsets, smart watches, smartphones, servers and other fields. In the future, it will appear in more wearable products such as smart glasses, 5G millimeter wave modules, smart cars, biomedicine and other applications that have special requirements for size. .
Using SiP technology can also solve the “Memory Wall” problem that plagues system performance bottlenecks and achieve better EMI Shielding functions. In addition, Zhao Jian, AVP of USI’s Advanced Process R&D Center and Miniature Module Business Division, pointed out that through heterogeneous integration, SiP can also reduce processes in back-end assembly plants, and more highly automated processes can be integrated at the front end, thereby reducing supply. Overall chain complexity.
The ultimate goal of SiP is to achieve fully integrated self-contained autonomous electronic systems. This means that the SiP will have independent power supplies, microprocessors, inputs, outputs, and passives, and be able to perform exactly the required functions without external wiring. The ideal SiP has no external pins (if it has its own power supply) or only 2 pins – for power and ground. However, the premise is that the power distribution network (PDN), signal integrity (SI) and thermal management, as well as the reliability of the system are all handled properly.
Chiplet will drive up R&D costs for heterogeneous integration
In addition, as the number of functional modules integrated increases and the chip size becomes larger, the most direct impact will be a reduction in yield. One of the solutions is to cut the chip into multiple chiplets, and then use the high-density interconnection provided by advanced packaging technology to integrate these chiplets in the same package. Presumably, this could reduce production costs while increasing yields.
Industry insiders always believe that Chiplet can also be regarded as a SiP technology, which is the commercialization of IP modules in SoCs.
The industry view is that the modular design scheme based on Chiplet will push up the research and development cost of next-generation heterogeneous integration technology and drive the further development of packaging technology. According to different price and performance requirements, Chiplet can provide a variety of package options. This trend is expected to make the front and back semiconductor processes that used to use different tools and equipment become more and more similar.
Challenges are also evident. For example, Fang Lizhi, deputy general manager of Licheng, pointed out earlier that in terms of cost reduction, the biggest cost risk factor of advanced packaging is to package faulty chips with normal chips, resulting in modules that cannot work normally. This is especially evident in wafer-to-wafer (W2W) packaging, where there is no way to lock KGD (known good die) and reject faulty die in advance.
As more and more single chips are integrated, the quality requirements for incoming chips will become more and more stringent. In addition, licensable IP makes assembling chips easier, but also more expensive.
Packaging technology innovation faces many challenges
Advanced packaging undoubtedly presents many new challenges. In addition to materials and equipment, as advanced packaging becomes more and more complex, existing EDA design tools need to solve many problems in completing advanced packaging design.
Ling Feng, founder and CEO of Xinhe Semiconductor, pointed out that between different chips, between chips and packages, there is a “wall” in the design and analysis of EDA tools. How to break the “wall” between the chip and the package, how to achieve the consistency of EDA platform data, complete the collaborative design of signals, power, heat, stress, etc., and how to complete the simulation analysis in a unified database, will become the further development of SiP technology. important driving force for development.
For the domestic industry, the situation is more severe and there are more challenges.
Santosh Kumar, chief analyst at research firm Yole Developpement, once pointed out that although the market size of advanced packaging is growing rapidly, the relationship of the supply chain will become more complex than ever. Many links in the industry chain have entered the system-in-package market, including IDM, foundry and EMS. In the future, this market will usher in more players, and substrates/PCBs and foundries may share some of the market pie of advanced packaging. Therefore, in addition to the diversified technical layout, packaging factories must also learn to respond more flexibly to the new industrial environment.
At present, there are a number of packaging and testing companies in the forefront of the industry, such as Changdian Technology, Tongfu Microelectronics, and Tianshui Huatian. Among them, Changdian Technology now has SiP that can compete with ASE, and Fan- OuteWLB, WLCSP, SiP, Bumping, FC-BGA and many other packaging technologies.
Industry experts believe that in the future, packaging and testing companies with complete system packaging and system module integration capabilities will be more likely to be favored by the market. Huachuang Securities also pointed out that in the context of the slowdown of Moore’s Law, the packaging link is becoming more and more important to improve the overall performance of the chip. With the development of advanced packaging in the direction of miniaturization and integration, the technical barriers continue to increase. In the future, the packaging and testing link may replicate the development path of the foundry link, that is, the market size of advanced packaging is rapidly increasing, and leading manufacturers with leading technologies will enjoy Maximum bonus.
Although domestic advanced packaging technology has made progress, it still faces many challenges. Data shows that in 2020, the global market share of China’s advanced packaging market output value is only 14.8%. Compared with the world-class packaging and testing enterprises, there is still a big gap in the comprehensive technical level in China. However, under the background of domestic substitution, packaging and testing, as a sub-industry with the most prominent advantages in my country’s semiconductor field, will continue to maintain a growth trend. New challenges and problems at the advanced packaging level are waiting for domestic manufacturers to break the situation.